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std.aarch64

AArch64 instructions a kernel needs: exception vectors, system registers, barriers for –target aarch64-freestanding; most need EL1

pub wfi :: fn()

waits for the next interrupt

pub wfe :: fn()

waits for an event (sev, an interrupt)

pub sev :: fn()
pub isb :: fn()

instruction barrier: what follows sees a system register just written

pub dsb :: fn()

data barriers over the whole system

pub dmb :: fn()
pub mask_interrupts :: fn()

masks debug, SError, IRQ and FIQ

pub unmask_interrupts :: fn()
pub breakpoint :: fn()

brk #0: a synchronous exception; the handler moves elr past it to go on

pub current_el :: fn() -> u64

the exception level running now: 0 to 3

pub read_mpidr :: fn() -> u64
pub read_cntpct :: fn() -> u64

the generic timer’s count and its frequency in Hz

pub read_cntfrq :: fn() -> u64
pub read_sctlr :: fn() -> u64

the translation table base and control registers, for paging

pub write_sctlr :: fn(v: u64)
pub write_ttbr0 :: fn(v: u64)
pub write_tcr :: fn(v: u64)
pub write_mair :: fn(v: u64)
pub ExceptionFrame :: struct {
x: [31]u64,
elr: u64,
spsr: u64,
esr: u64,
far: u64,
}

the registers when the exception came, saved by the vectors; elr is where it goes back to (a handler may change it and the x registers), esr says why (bits 26-31 the class) and far is the faulting address of an abort

pub SYNC :: 4u64

the second parameter of a handler: which of the 16 vectors (a kind from the current level)

pub IRQ :: 5u64
pub FIQ :: 6u64
pub SERROR :: 7u64
pub set_exception_handler :: fn(handler: extern fn(*ExceptionFrame, u64))

every exception at EL1 goes to handler, an ordinary function: it gets the saved registers, and the exception goes back to frame.elr when it returns

pub exception_class :: fn(esr: u64) -> u64

the exception class of an esr: 0x3C a brk, 0x15 an svc, 0x24 and 0x25 data aborts, …